1. Technical Field
The present invention relates to memory arrays in general, and, in particular, to content-addressable memory random address memory (CAMRAM) memory arrays. Still more particularly, the present invention relates to an apparatus for detecting multiple hits in a CAMRAM memory array.
2. Description of the Related Art
Content-addressable memories (CAMs) are commonly utilized in a cache memory for functions such as directory look-up. During normal operations, a CAM compares an input address with all internally stored addresses. If any one of the internally stored addresses matches the input address, then the CAM signals that there is an address match (or a xe2x80x9chitxe2x80x9d in cache memory terminology). Match signals from a CAM can be utilized to drive a global wordline within an associated data array of the cache memory for enabling a specific data word to be output. Based on a similar concept, a CAMRAM memory array includes a CAM to scan a random address memory (RAM) to find a matching data pattern.
Integrated circuit memory devices, such as CAMRAM memory arrays, have been becoming smaller and smaller from one generation to another. Incidentally, the sizes of memory cells within an integrated circuit memory device have also gotten smaller and smaller. One of the disadvantages with small memory cells is that the soft error rate (SER) increases accordingly. In order to overcome the problem with SER, parity techniques have been commonly employed in integrated circuit memory devices. Another method for combating the SER problem in integrated circuit memory devices is the incorporation of a multi-hit detector.
The present disclosure relates to a multi-hit detector for detecting multiple hits in a CAMRAM memory array.
In accordance with a preferred embodiment of the present invention, a CAMRAM includes a random address memory, a content-addressable memory, a set of index address lines and a set of multiple-hit detection address lines. The index address lines and the multiple-hit detection address lines are complementarily connected to a set of matchlines via transistors. Coupled to the index address lines and the multiple-hit detection address lines, a comparator circuit is capable of outputting a multi-hit signal when more than one of the matchlines are turned on simultaneously during an address comparison operation.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.